1. Field of the Invention
The present invention relates to a semiconductor device having a structure which is adaptable to various types of devices, mainly a semiconductor device having an SOI (silicon on insulator) structure, as well as a manufacturing method for the same.
2. Description of the Background Art
FIGS. 102 to 111 are cross sectional views showing a manufacturing method for a conventional MOS transistor formed on an SOI substrate. Hereinafter, the manufacturing method is described with reference to these drawings.
First, as shown in FIG. 102, a buried oxide film 2 having a film thickness of 10 nm to 1000 nm and a silicon layer 3 having a film thickness of 30 nm to 200 nm are formed in sequence on a silicon support substrate 1, which is a semiconductor substrate, and thereby, an SOI substrate (structure) composed of the silicon support substrate, the buried oxide film and the silicon layer 3 is obtained. Furthermore, a silicon oxide film 7 having a film thickness of 5 nm to 400 nm is formed on the silicon layer 3, and a silicon nitride film 4 having a film thickness of 10 nm to 200 nm is formed on the silicon oxide film 7.
Next, as shown in FIG. 103, a resist film is applied on the entire surface, and a resist pattern 9 (pattern for element isolation) for forming trenches is formed through photolithography.
After that, as shown in FIG. 104, the silicon nitride film 4, the silicon oxide film 7 and the silicon layer 3 are etched using the resist pattern 9 as a mask to form trenches. This etching process is performed in such a manner that the silicon layer 3 partially remains (partial trench isolation (PTI)). Furthermore, the inner walls of the trenches in the silicon layer 3 are oxidized to form inner wall oxide films 25 having a film thickness of 5 nm to 50 nm on the exposed surfaces of the silicon layer 3. Here, the process for forming inner wall oxide films 25 may be omitted.
Then, as shown in FIG. 105, silicon oxide films 10 bury in the trenches an annealing process at 500° C. to 1300° C. is performed. Then, a CMP (chemical mechanical polishing) process is performed using the silicon nitride film 4 as a stopper, and thereby, the silicon oxide films 10 are flattened. Here, the annealing process may be omitted.
Subsequently, as shown in FIG. 106, after the silicon oxide films 10 is etched to set the film thickness of the silicon oxide films 10 to a predetermined thickness, as shown in FIG. 107, the silicon nitride film 4 and a silicon oxide film 6 are removed.
Next, as shown in FIG. 108, silicon oxide films 12 are formed on the exposed surfaces of the silicon layer 3 between the silicon oxide films 10 and 10.
After that, as shown in FIG. 109, a polysilicon film is formed and patterned through photolithography, and thereby, gate electrodes 13 are formed, silicon oxide film spacers 14 are formed on the sides of the gate electrodes 13, and after that, impurity ions 15 are injected into the silicon layer 3 using the gate electrodes 13 and the silicon oxide film spacers 14 as a mask to form diffusion regions 37 which later become extension & pocket regions.
Then, as shown in FIG. 110, silicon oxide film side walls 16 and silicon nitride film side walls 17 are formed in sequence on the sides of the silicon oxide film spacers 14, and impurity ions are injected using the gate electrodes 13, the silicon oxide film spacers 14, the silicon oxide film side walls 16 and the silicon nitride film side walls 17 as a mask to form source/drain regions 38. At this time, the source/drain regions 38 penetrate through the silicon layer 3 to reach the silicon layer 3, so that the diffusion regions 37 mainly beneath the silicon nitride film side walls 17 becomes extension/pocket regions 37e. Furthermore, metal silicide regions 18 and 29 of cobalt (Co) silicide and the like are formed on the gate electrodes 13 and the source/drain regions 38, respectively.
Finally, as shown in FIG. 111, a silicon nitride film 42 is formed on the entire surface, and after the formation of an interlayer insulating film 19 on the silicon nitride film 42, a CMP process is performed to flatten the interlayer insulating film 19. In addition, a resist pattern (not shown) for etching is formed through photolithography, and contact holes are formed using this resist pattern as a mask, the contact holes are filled in with a metal so that metal plugs 20 are formed. Furthermore, the metal plugs 20 are electrically connected to the interlayer insulating film 19 to form metal wires 21. Al (aluminum), copper (Cu) and the like are considered as materials of the metal wires 21.
In this manner, MOS transistors are formed on the SOI substrate. The body regions of these MOS transistors are electrically connected to body contact regions (not shown) to which a predetermined body potential is provided via the silicon layer 3 beneath the silicon oxide films 10.
When the film thickness of the SOI film (film thickness of the silicon layer 3) becomes smaller by scaling, there is a problem that increases in the body resistance and cannot satisfy characteristics required for the devices used in I/O circuits or analog circuits. In addition, in the case where the thickness of the SOI film is great, the larger parasitic capacitance decrease in speed performance, and thus there is a problem that cannot satisfy speed characteristics required for the devices used in logic circuits and the like.
As a semiconductor device for solving these problems, there are transistors formed to have an SOI structure as that disclosed in, for example, Japanese Patent Application Laid-Open No. 2005-19453. According to the structure disclosed in Japanese Patent Application Laid-Open No. 2005-19453, an SOI structure can be cited, where a first semiconductor layer is provided on top of a buried insulating film in a memory cell region, and a second semiconductor layer is provided on a buried insulating film in a peripheral circuit region. The first and second semiconductor layers are made to have a different film thickness, so that transistors in the memory cell region become of a complete depletion type and transistors in the peripheral circuit region become of a partial depletion type.
However, there is a problem that cannot satisfy requirements for various device characteristics used in a variety of circuits even if semiconductor layers with an SOI structure having simply two types of SOI film thicknesses is provided.